Digitally controlled threshold adjustment circuit

ABSTRACT

Embodiments of threshold adjustment circuits are disclosed. An example circuit includes a first differential pair of first and second thin oxide transistors. The first and second thin oxide transistors decrease a DC voltage component of a first or second component of an input signal of the circuit. The example circuit further includes a second differential pair of third and fourth thin oxide transistors. The second and third thin oxide transistors increase a DC voltage component of the first or the second component of the input signal. The example circuit also includes a power supply for providing a supply voltage to the circuit, the power supply having a voltage level above a reliability level of the thin oxide transistors. In the example circuit, each of the differential pair thin oxide transistors is switched by a signal that keeps each of the first, second, third, and fourth thin oxide transistors operating in saturation.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.11/117,767, filed Apr. 28, 2005, entitled “DIGITALLY CONTROLLEDTHRESHOLD ADJUSTMENT CIRCUIT,” now U.S. Pat. No. ______. U.S. patentapplication Ser. No. 11/117,767 is incorporated by reference herein init entirety.

TECHNICAL FIELD

This application is related to electronic circuits, and moreparticularly to a digitally controlled threshold adjustment circuit.

BACKGROUND

In optical communications, the transmitted signal over a fiber opticlink will exhibit an asymmetric eye opening. For example, as depicted inFIG. 1A, a transmitted signal exhibits an asymmetric eye relative tovertical threshold of its sampler. As known to one skilled in the art,LOGIC 0 has significantly less vertical margin compared to LOGIC 1 dueto the shown asymmetry. One way to alleviate the problem is to adjustthe Direct Current (DC) component voltage levels of the single-endedsignals Outp and Outn in order to level out the vertical margins of Outpand Outn with respect to the sampler. In the example of FIG. 1A, one candecrease the DC component voltage level of Outp, or increase the DCcomponent voltage level of Outn to substantially reduce the asymmetriceye opening. This adjustment of the DC component voltage levels can alsobe done by both decreasing the DC component voltage level of Outp andincreasing the DC component voltage level of Outn simultaneously and ina differential manner for half the amount at each side.

In order to optimize the performance of the receiver to capture theincoming signal with an asymmetric eye opening, it is required toestablish a threshold adjustment mechanism that can adjust the verticaleye opening of the signal to a more balanced and symmetric shape. Asseen in FIG. 1B, after threshold adjustment, vertical margin of LOGIC 0is increased and vertical margin of LOGIC 1 is reduced, compared to thesame margins in FIG. 1A. Since the minimum margin level determines thereceiver performance, it is always desirable to have balanced verticalmargins or symmetric eye opening. Threshold adjustment circuits aredesigned to achieve a more symmetric eye opening in the incomingsignals.

FIG. 2 is a conventional threshold adjustment circuit. As depicted inFIG. 2, two current-based Digital to Analog Converters (DACs) aredirectly connected to Outp and Outn decrease the DC component voltagelevel of Outp, or increase the DC component voltage level of Outn.However, in this configuration, the DACs' outputs have significantcapacitive loading due to large DAC transistors needed to generate therequired maximum current for the threshold adjustment. In this case, theDACs heavily load Outp and Outn and thus causing bandwidth limitation.Moreover, two current DACs occupy large silicon area.

In another typical threshold adjustment circuit shown in FIG. 3, twoswitches Sp and Sn connected to a single current DAC are used to connectthe single DAC to Outp or Outn, alternatively. This scheme also suffersfrom bandwidth limitation due to heavy capacitive loading of Outp andOutn. Switches Sp and Sn can be considered as transistors in trioderegion when turned ON. In the triode region, Sp and Sn exhibit largedrain capacitances, as well as low drain-to-source resistance (Rds). Dueto low Rds resistance, majority of the DAC output capacitance will alsobe observed at Outp and Outn. In a case where low voltage transistorsare being used with a supply voltage (VDD) above the reliability voltagelimit, Sp and Sn switches may exhibit reliability problems due to overthe limit terminal voltages.

All of above conventional implementations introduce bandwidthlimitations on the signal path. In addition, the above conventionalthreshold adjustment circuits require further improvements to avoid anyreliability problems if low voltage transistors are used with a powersupply voltage above their reliability voltage limit. These circuitsalso occupy large silicon area.

Therefore, there is a need for an accurate and reliable thresholdadjustment circuit that does not impose any significant bandwidthreduction due to loading of the signal path.

SUMMARY

In one embodiment, the present invention is a threshold adjustmentcircuit including: a current digital-to-analog converter (DAC) forsupplying or sinking a varying current; a differential pair of thinoxide transistors coupled to the DAC and coupled together at a commonsource node; a supply voltage having a voltage level above reliabilityof the pair of thin oxide transistors; and a third transistor formaintaining voltage of the common source node above a predeterminedlevel and to disable the threshold adjustment circuit, wherein the bulkand source of each of the differential pair thin oxide transistors iscoupled to the common source node and each of the differential pair thinoxide transistors is switched by a signal having an ON voltage level sothat one of the thin oxide transistors is in saturation region andhaving an OFF voltage level so that the other thin oxide transistor isOFF but within its reliability limit.

In one embodiment, the present invention is a circuit for thresholdadjustment of an input signal having a first and a second component. Thethreshold adjustment circuit includes: a first differential pair offirst and second thin oxide transistors for decreasing a DC voltagecomponent of the first or second component of the input signal; a seconddifferential pair of third and fourth thin oxide transistors forincreasing a DC voltage component of the first or the second componentof the input signal; a power supply for providing a supply voltagehaving a voltage level above reliability of the thin oxide transistors,wherein each of the differential pair thin oxide transistors is switchedby a signal that keeps each of the first, second, third, and fourth thinoxide transistors in saturation region.

In one embodiment, the present invention is a threshold adjustmentcircuit for a differential input signal. The threshold adjustmentcircuit includes: means for decreasing DC voltage component of eitherside of the differential input signal; means for increasing the DCvoltage component of either side of the differential input signal; andmeans for generating a signal for switching between means for decreasingthe DC voltage component and means for increasing the DC voltagecomponent voltage of the input signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a timing diagram of a differential asymmetric incomingsignal, before threshold adjustment;

FIG. 1B is a timing diagram of a differential asymmetric incomingsignal, after threshold adjustment;

FIG. 2 is a conventional threshold adjustment circuit;

FIG. 3 is another conventional threshold adjustment circuit;

FIG. 4 is an exemplary circuit diagram of a threshold adjuster fordecreasing DC component voltages, according to one embodiment of thepresent invention;

FIG. 5 is an exemplary circuit diagram of a current steering DAC,according to one embodiment of the present invention;

FIG. 6 is an exemplary circuit diagram of an alternative implementationof disabling scheme of a threshold adjuster for increasing anddecreasing DC component voltages, according to one embodiment of thepresent invention;

FIG. 7 is an exemplary circuit diagram of a threshold adjuster,according to one embodiment of the present invention; and

FIG. 8 is an exemplary circuit diagram of a threshold adjuster forincreasing DC component voltages, according to one embodiment of thepresent invention.

DETAILED DESCRIPTION

In one embodiment, the present invention is a digitally controlledthreshold adjustment circuit which does not impose any significantbandwidth reduction due to loading of the signal path. Since the circuitis digitally controlled, it can easily be incorporated into an adaptivealgorithm that can automatically find the optimal point for sampling,without user intervention.

FIG. 4 is an exemplary circuit diagram of a threshold adjuster,according to one embodiment of the present invention. As depicted inFIG. 4, a threshold adjustment circuit 42 is connected to currentsumming nodes 43 and 44, which generate Outp and Outn, respectively. Asan example, threshold adjustment circuit 42 can be connected to Outp andOutn at the output of a gain stage which includes a trans-conductance(GM) 41 sinking current from load impedances (R_(LOAD)) 47 a and 47 b.Threshold adjustment circuit 42 includes a current DAC 45, whichgenerates a threshold current 46 (I_(threshold)). In one embodiment, athermometer coded current steering DAC is utilized to implement the DAC45, as depicted in FIG. 5.

FIG. 5 is an exemplary circuit diagram of a current steering DAC,according to one embodiment of the present invention. As shown,transistor M_(b) biased by a current I_(unit) supplies a bias voltageV_(bias). Each of the transistors M₀ to M_(K) is turned on by respectiveswitches S₀ to S_(K) that are driven by CONT<0> to CONT<K>,respectively. Depending on the digital code CONT<k:0>, current I_(out)(I_(threshold)) varies from 0 to its maximum required value in linearand monotonic steps. The maximum I_(threshold) value can be calculatedas (k+1)I_(unit). In addition, the linear step size is I_(unit). The DACis called a thermometer DAC in this case, because the current sourcesswitch one-at-a-time only.

Referring back to FIG. 4, NMOS transistors Mp and Mn are used in theirsaturation regions to sink all of I_(threshold) to either Outp or Outn.In other words, NMOS transistors Mp and Mn are used for polarityselection of threshold adjustment. If Mp is turned ON (saturationregion), then Mn is turned OFF sending I_(threshold) to Outn. Likewise,if Mn is turned ON (saturation region), then Mp is turned OFF sendingI_(threshold) to Outp. If I_(threshold) is sunk into Outn, the DCvoltage component of Outn decreases by the amount that corresponds tothe voltage drop generated by I_(threshold) on R_(LOAD) 47 a. That is,the selected current from the DAC induces a voltage drop across theloads, which in turn reduces the DC voltage component of Outn.

In the above embodiment, NMOS transistors Mp and Mn, as well astransistors in the DAC are all low voltage transistors. Furthermore, thepower supply VDD is used above the reliability voltage limit of the lowvoltage transistors. Using low voltage transistors is preferred toobtain the maximum trans-conductance with minimum area and loading.Using a VDD above the reliability voltage limit is also preferred toachieve higher speed for circuit components such as drivers, flip-flops,etc. If the low voltage transistors are used with a VDD above theirreliability voltage limit, a careful biasing and proper operation of thelow voltage transistors should be taken into account in the design ofthe circuit. In other words, the design should ensure that the voltagedrops across the terminals of every low voltage transistor be withintheir reliability voltage limit.

In operation, when Mp is turned ON, input voltage Vbp(ON) is pulled to apredetermined voltage level above the threshold voltage V_(TH) of Mp,but lower than power supply VDD, to keep Mp in saturation region, evenif I_(threshold) goes to its maximum level. A saturation region of aNMOS transition occurs when VD>VG−V_(TH) of the transistor. Whenoperating in the saturation region, a transistor has a high impedancebetween its source and drain. This high impedance decouples the outputcapacitance of the DAC from the R_(load). If Vbp(ON) was selected ashigh as VDD, then Mp would go into triode region where not only itsdrain capacitance increases, but also, the DAC output capacitance wouldbe added to the Outn node. Increased drain capacitance due to Mpentering into triode region would decrease the bandwidth at node Outn.In one embodiment, the input voltages Vbp and Vbn are digitallycontrolled.

Likewise, when Mn is turned ON, input voltage Vbn(ON) is pulled to apredetermined voltage level, lower than power supply VDD to keep Mn insaturation region, even if I_(threshold) goes to its maximum level.Similar to Vbp(ON), if Vbn(ON) was selected as high as VDD, then Mnwould go into triode region where its drain capacitance increasessignificantly. Again, increased drain capacitance due to Mn enteringinto triode region would decrease the bandwidth at node Outp. In oneembodiment, the predetermined voltage level of the input voltageVbp(ON)/Vbn(ON) is generated using a resistor voltage divider (notshown) to limit the Vbp(ON)/Vbn(ON) voltage to a voltage lower than VDD,so that Mp/Mn operate in their saturation regions and stay within theirreliability limits. Similarly, the predetermined voltage level of theinput voltages Vbp(OFF)/Vbn(OFF) is generated using a resistor divider(not shown) to limit the Vbp(OFF)/Vbn(OFF) to a voltage higher than GND,so that Mp/Mn operate in their OFF regions and stay within theirreliability limits.

Further, bulk nodes of Mp and Mn are tied to a common source nodeV_(SOURCE) to prevent drain-to-bulk voltage (VDB) from going above thereliability voltage limit. Likewise, when the bulk node is tied tosource node the bulk-to-source voltage (VBS) becomes zero. Thus, thebody effect on threshold voltage V_(TH) of the transistor, which is afunction of VBS, is also eliminated. This decreases the gate-to-sourcevoltage (VGS) of the respective transistor for a given current density.Since VGS is reduced, this results in relaxing the headroom requirementof DAC transistors.

When Mp is turned OFF, Vbp(OFF) is pulled to a predetermined voltagelevel below the threshold voltage V_(TH) of Mp, but higher than groundvoltage (GND) to keep drain-to-gate voltage (VDG) of Mp below thereliability voltage limit. Similarly, when Mn is turned OFF, Vbn(OFF) ispulled to a predetermined voltage level below the threshold voltageV_(TH) of Mn, but higher than GND to keep VDG voltage of Mn below thereliability voltage limit. However, if Vbn(OFF) is selected too low,such as GND, VDG of Mp and Mn would increase above its limit, whichcould cause reliability issues for Mp and Mn.

When the threshold adjustment circuit is disabled, the DC componentvoltage levels of Outp and Outn do not need to be adjusted. In oneembodiment, both Mp and Mn are turned on resulting in sinking a smallamount of current such as, but not limited to, I_(unit) into Mp and Mn.However, keeping Mp and Mn both ON will have some disadvantages. Due tomismatch between Mp and Mn, I_(threshold) will not be evenly sunk intoOutp and Outn, which can cause a leaky and undesired thresholdadjustment. Depending on the amount of current left sinking, DCcomponent voltage levels of both Outp and Outn will go down and thusdecrease the headroom for GM (DAC) stage. Moreover, if both Mp and Mnare left ON (in their saturation regions), then Rds(Mp)+Rds(Mn) decreasethe output impedance R_(LOAD) resulting in a decrease in the gain.

In one embodiment, when the threshold adjustment circuit is disabled,both Mp and Mn are turned off and another current passage path iscreated by switching on the transistor M_(shut). The reason for creatinganother current passage path is to keep the common source node voltageV_(SOURCE) of Mp and Mn above a certain level so that thedrain-to-source voltage (VDS) of Mp and Mn can be kept within thereliability voltage limit. Thus, a small amount of current such as,I_(unit) is left sinking into M_(shut) to keep V_(SOURCE) above acertain level. Since M_(shut) is not in the critical signal path, a highvoltage transistor for M_(shut) is used such that it does not requireany special biasing for M_(shut), since VDD is within the reliabilityvoltage limit of the high voltage transistor M_(shut).

If high voltage transistors are not available in the process and/orM_(shut) should also be protected against over the limit terminalvoltages, an alternative implementation of disabling scheme isillustrated in FIG. 6. Resistor R is used to limit the VDS voltage ofM_(shut). In addition, the gate voltages of M_(shut), DISABLE and ENABLEvoltages, have predetermined values to avoid any over the limit terminalvoltages for M_(shut) and M_(ena) whether they are turned ON or OFF. Oneor more NMOS or PMOS transistors can be utilized to implement resistorR. Transistor Mi that is biased by V_(BIAS) operates as a currentsource.

Although the threshold adjustment circuit is described using NMOStransistors only, those skilled in the art understand that the thresholdadjustment circuit can be implemented using only PMOS transistors orusing both NMOS and PMOS transistors.

The threshold adjustment circuit of FIG. 4 is utilized to decrease theDC voltage components of Outn or Outp. FIG. 7 is an exemplary circuitdiagram of a threshold adjustment circuit that decreases the DC voltagecomponents of Outn and Outp and increases the DC voltage components ofOutn and Outp, resulting in a more uniform signal, as shown in FIG. 1B.

As illustrated in FIG. 7, a first threshold adjustment circuit 73operates similar to the threshold adjustment circuit described in FIG. 4to decrease and/or increase the DC voltage components of GM 72 outputs,Outn and Outp. A second threshold adjustment circuit 74 operates in acomplementary way to the threshold adjustment circuit 73 to increaseand/or decrease the DC voltage components of Outn and Outp also. Asignal NV_(shut) which may be the inverted signal V_(shut) is used toshut the second threshold adjustment circuit 74. Each of the thresholdadjustment circuits 73 and 74 include a DAC that is controlled bycontrol signals CONT<k:0>. The control signals CONT<k:0> to each of thethreshold adjustment circuits 73 and 74 may be the same or different,depending on the amount of current requirements to reduce the asymmetriceye opening, shown in FIG. 1A. In one embodiment there is only one DACthat is supplying/sinking current to each of the threshold adjustmentcircuits 73 and 74. Load resistors 75 a and 75 b are similar to thoseload resistors of FIG. 4. An exemplary embodiment of the thresholdadjustment circuit 74 is shown in FIG. 8.

FIG. 8 is an exemplary circuit diagram of a threshold adjustment circuitfor increasing DC voltage components, according to one embodiment of thepresent invention. The circuit is similar to the threshold adjustmentcircuit of FIG. 4 in operation, however, it uses PMOS transistors,instead of NMOS transistors and supplies a current I_(threshold), ratherthan sinking the current, to the loads.

The threshold adjustment circuit is coupled to Outp and Outn at theoutput of a GM 82 sourcing current from load impedances (R_(LOAD)) 85 aand 85 b. DAC 84 generates a threshold current 86 (I_(threshold)).Again, depending on the digital code CONT<k:0>, current I_(threshold)varies from 0 to its maximum required value in linear and monotonicsteps.

PMOS transistors Mpp and Mpn driven by inputs Vbn and Vbp are used intheir saturation regions to send all of I_(threshold) to either Outp orOutn. If Mpp is turned ON (saturation region), then Mpn is turned OFFsending I_(threshold) to Outp. Likewise, if Mpn is turned ON (saturationregion), then Mpp is turned OFF sending I_(threshold) to Outn. IfI_(threshold) is supplied into Outn, DC voltage components of Outnincreases by the amount that corresponds to the voltage drop generatedby I_(threshold) on R_(LOAD) 85 b. In the above embodiment, PMOStransistors Mpp and Mpn, as well as transistors in the DAC are all lowvoltage transistors. However, M_(pshut) transistor may be a thick oxidetransistor. If high voltage transistors are not available in the processand/or M_(pshut) should also be protected against over the limitterminal voltages, the alternative implementation of disabling scheme ofFIG. 6, that is, using a resistor R to limit the VDS voltage of Mpshutmay be used.

Control signal NV_(shut) is used to disable the threshold adjustmentcircuit by turning the PMOS transistor M_(pshut) ON while both Mpn andMpp are OFF. Also, the bulks of Mpp and Mpn are connected to the commonsource node V_(psource) and Vbp and Vbn voltages are set properly forturning Mpp and Mpn ON/OFF to avoid any voltage drop across theterminals of Mpp and Mpn rising below the reliability limit.

It will be recognized by those skilled in the art that variousmodifications may be made to the illustrated and other embodiments ofthe invention described above, without departing from the broadinventive scope thereof. It will be understood therefore that theinvention is not limited to the particular embodiments or arrangementsdisclosed.

1. A circuit for threshold adjustment of an input signal having a firstand a second component, the circuit comprising: a first differentialpair of thin oxide transistors for decreasing a DC voltage component ofthe first or second component of the input signal, the firstdifferential pair of transistors including a first transistor and asecond transistor; a second differential pair of thin oxide transistorsfor increasing a DC voltage component of the first or the secondcomponent of the input signal, the second differential pair oftransistors including a third transistor and a fourth transistor; apower supply for providing a supply voltage having a voltage level abovea reliability level of the first and second pairs of thin oxidetransistors, wherein each of the differential pair thin oxidetransistors is switched by a signal such that the first, second, third,and fourth transistors operate in saturation.
 2. The circuit of claim 1,wherein respective bulk nodes and source nodes of each of the first andsecond transistors are coupled to a first common source node, andrespective bulk nodes and source nodes of each of the third and fourthtransistors are coupled to a second common source node.
 3. The circuitof claim 1, wherein the first transistor and the second transistorcomprise NMOS transistors.
 4. The circuit of claim 1, wherein the thirdtransistor and the fourth transistor comprise PMOS transistors.
 5. Thecircuit of claim 1, wherein the circuit is configured to: receive afirst disable signal to disable the first differential pair; and receivea second disable signal to disable the second differential pair.
 6. Athreshold adjustment circuit for adjusting a differential input signalcomprising: means for decreasing respective DC voltage components of atleast one side of the differential input signal; means for increasingthe respective DC voltage components of at least one side of thedifferential input signal; and means for generating a signal to switchbetween the means for decreasing the respective DC voltage componentsand the means for increasing the respective DC voltage components of thedifferential input signal.
 7. The circuit of claim 6, further comprisingmeans for disabling the means for decreasing the respective DC voltagecomponents.
 8. The circuit of claim 6, further comprising means fordisabling the means for increasing the DC voltage components.
 9. Thecircuit of claim 6, wherein the means for increasing the respective DCvoltage components comprises a thermometer coded current steeringdigital-to-analog converter.
 10. The circuit of claim 6, wherein themeans for decreasing the respective DC voltage components comprises athermometer coded current steering digital-to-analog converter.
 11. Thecircuit of claim 6, wherein the means for increasing the respective DCvoltage components comprises: a differential pair of thin oxidetransistors; and a switch configured to disable the differential pair ofthin oxide transistors.
 12. The circuit of claim 6, wherein the meansfor decreasing the respective DC voltage components comprises: adifferential pair of thin oxide transistors; and a switch configured todisable the differential pair of thin oxide transistors.